| Popis: |
This paper presents a new spread spectrum clock generator (SSCG) circuit for EMI reduction. The proposed design adopts a standard integer-N phased locked loop (PLL) with two dual-voltage-controlled oscillators (VCOs). A frequency modulation loop is implemented with a digital frequency limit detector to direct the spectrum-spreading profile. An integrator is applied to generate the triangular modulation signal. Comparing with some recent designs [1,2,3,4] in the literature, the spread spectrum clock generator in this paper is simple and area efficient. |
