Substrate Isolation Options Effect on HV Latch-up
| Autor: | David Marreiro, Vladislav Vashchenko |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Electrostatic discharge Materials science business.industry Semiconductor device modeling 020206 networking & telecommunications Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Test method 01 natural sciences law.invention Power (physics) CMOS law 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Optoelectronics Electric potential business Voltage Light-emitting diode |
| Zdroj: | 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD). |
| DOI: | 10.23919/eos/esd.2018.8509741 |
| Popis: | The novel wafer-level test method is used to study HV latch-up specifics through comparisons between two most common power analog processes - Extended CMOS and BCD. The dependence of the critical injector-victim voltage upon the injector-victim spacing is analyzed toward practically useful high-and low-side injection HV latch-up regularities. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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