A 14 nm Embedded STT-MRAM CMOS Technology

Autor: Virat Mehta, Devika Sil, V. Katragadda, E. R. Evarts, J. DeBrosse, Sanjay Mehta, Richard G. Southwick, C. Long, Abraham Arceo, Dominik Metzler, Theodorus E. Standaert, A. Gasasira, C.-C. Yang, Son Nguyen, Raghuveer R. Patlolla, P. Nieves, D. Houssameddine, E. R. J. Edwards, V. Pai, Thomas M. Maffitt, Daniel C. Worledge, Michael Rizzolo, James Chingwei Li, O. van der Straten, J. Fullam, J. Morillo, Yaocheng Liu, Heng Wu, R. Johnson, Chu Isabel Cristina, J. M. Slaughter, T. Levin, S. McDermott, R. Pujari, Guohan Hu, James J. Demarest, Daniel C. Edelstein, Ashim Dutta, Yutaka Nakamura, M. Iwatake, M.R. Wordeman
Rok vydání: 2020
Předmět:
Zdroj: 2020 IEEE International Electron Devices Meeting (IEDM).
Popis: We present the first Embedded Spin-Transfer-Torque MRAM (eMRAM) technology in a 14 nm CMOS node. A novel integration supports the highest eMRAM density (0.0273 um2 cell size), optimal magnetic tunnel junction (MTJ) placement between M1-M2 for performance and density, and the lowest-cost integration scheme, with only 3 added mask levels (2 critical + 1 non-critical) and a single added electrode module. An advanced 400°C-compatible MTJ stack is read and written by innovative reference-cell sensing circuitry. We demonstrate digital functionality and write performance down to 4 ns, with companion parametric analysis for magnetoresistance, switching voltage, retention, and endurance cycling. Finally, we checked the 14 nm eMRAM hardware BEOL EM and TDDB at the critical levels, verifying good reliability after the embedding process.
Databáze: OpenAIRE