16.1 A 12b 18GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Amplifier and Background Calibration
| Autor: | Matthew D. McShea, Huseyin Dinc, Ahmed Mohamed Abdelatty Ali, Joel Prabhakar, Mohit Kumar, Ryan Bunch, Scott Gregory Bardsley, Scott Puckett, Paritosh Bhoraskar, Christopher Daniel Dillon |
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| Rok vydání: | 2020 |
| Předmět: |
Interleaving
Sampling (signal processing) Computer science Amplifier 020208 electrical & electronic engineering Bandwidth (signal processing) 0202 electrical engineering electronic engineering information engineering Electronic engineering 020207 software engineering 02 engineering and technology Wideband Capacitance |
| Zdroj: | ISSCC |
| Popis: | High sample rate ADCs with high input bandwidth and low power consumption enable direct RF sampling, more integration, flexibility and lower cost for communication, instrumentation and other applications. The state of the art of interleaved RF converters enables up to 10GS/s with 12-14b of resolution [1]–[4]. However, to increase the sample rate, the number of interleaved sub-ADCs tends to increase, which degrades the interleaving spurs due to sampling time and bandwidth mismatch, increases the input capacitance, reduces the input bandwidth, and increases the power consumption of the ADC. Randomization of the interleaved sub-ADCs helps alleviate the impact of the interleaving spurs, but that degrades the noise and increases power consumption in a manner that gets progressively worse as the input frequency and number of interleaved sub-ADCs increase [1]. |
| Databáze: | OpenAIRE |
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