Efficient design of continuous time linear equalization for loss dominated digital links
| Autor: | Torsten Reuschel, Christian Schuster, Jan B. Preibisch |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Engineering business.industry Pole–zero plot 020206 networking & telecommunications Context (language use) 02 engineering and technology Trial and error Network topology 01 natural sciences Data link Frequency domain 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Electronic engineering business Degradation (telecommunications) Communication channel |
| Zdroj: | 2017 IEEE 21st Workshop on Signal and Power Integrity (SPI). |
| DOI: | 10.1109/sapiw.2017.7943999 |
| Popis: | Signal degradation in high-speed data links can be mitigated by means of channel equalization. One preferred choice in conjunction with other techniques is the Continuous Time Linear Equalizer (CTLE) due to its effectiveness. Although CTLE being common technology, adaptation of design parameters regularly relies on trial and error. This work proposes a simple, yet very effective method for CTLE design, referred to as matched CTLE (mCTLE). It advocates channel characterization in the frequency domain which is crucial for the placement of CTLE poles and zeros. Demonstration and discussion based on typical interconnect topologies illustrate the novel approach in the context of existing literature. |
| Databáze: | OpenAIRE |
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