Addressing Defect Coverage through Generating Test Vectors for Transistor Defects
| Autor: | Shin-ya Kobayashi, Kewal K. Saluja, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu |
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| Rok vydání: | 2009 |
| Předmět: |
Computer science
business.industry Applied Mathematics Transistor Electrical engineering Test compression Hardware_PERFORMANCEANDRELIABILITY Integrated circuit Automatic test pattern generation Fault (power engineering) Computer Graphics and Computer-Aided Design law.invention law Test set Signal Processing Benchmark (computing) Electronic engineering Electrical and Electronic Engineering business Electronic circuit |
| Zdroj: | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :3128-3135 |
| ISSN: | 1745-1337 0916-8508 |
| Popis: | Shorts and opens are two major kind of defects that are most likely to occur in Very Large Scale Integrated Circuits. In modern Integrated Circuit devices these defects must be considered not only at gate-level but also at transistor level. In this paper, we propose a method for generating test vectors that targets both transistor shorts (tr-shorts) and transistor opens (tr-opens). Since two consecutive test vectors need to be applied in order to detect tr-opens, we assume launch on capture (LOC) test application mechanism. This makes it possible to detect delay type defects. Further, the proposed method employs existing stuck-at test generation tools thus requiring no change in the design and development flow and development of no new tools is needed. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method by providing 100% fault efficiency while the test set size is still moderate. |
| Databáze: | OpenAIRE |
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