Reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2nd generation high-k/metal gate transistors

Autor:	Abdur Rahman, J.-Y. Yeh, M. Agostinelli, K. Phoa, G. Curello, P. Bai, Joodong Park, Curtis Tsai, Hafez Walid M, C.-H. Jan, K. Komeyli, H. Deshpande, J. Xu
Rok vydání:	2011
Předmět:	Engineering business.industry Transistor Electrical engineering Time-dependent gate oxide breakdown law.invention Reliability (semiconductor) CMOS law Logic gate Electronic engineering System on a chip Metal gate business High-κ dielectric
Zdroj:	2011 International Reliability Physics Symposium.
Popis:	Extensive reliability characterization of a state of the art 32nm strained HK/MG SoC technology with triple transistor architecture is presented here. BTI, HCI and TDDB degradation modes on the Logic and I/O (1.2V, 1.8V and 3.3V tolerant) transistors are studied and excellent reliability is demonstrated. Importance of process optimizations to integrate robust I/O transistors without degrading performance and reliability of Logic transistors emphasized. Finally, Intrinsic and defect reliability monitoring for HVM are addressed.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::7ad3ffc66cc85e2e246a975e7733e28e https://doi.org/10.1109/irps.2011.5784531 Zobrazit plný text záznamu