A Next-Generation Cryogenic Processor Architecture
| Autor: | Jangwoo Kim, Gyu-hyeon Lee, Seongmin Na, Dongmoon Min, Ilkwon Byun |
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| Rok vydání: | 2021 |
| Předmět: |
Computer science
business.industry Clock rate 02 engineering and technology Cryogenics 020202 computer hardware & architecture Microarchitecture Power (physics) Computer Science::Hardware Architecture Hardware and Architecture Embedded system 0202 electrical engineering electronic engineering information engineering Cache Electrical and Electronic Engineering Performance improvement business Electrical efficiency Cryogenic processor Software |
| Zdroj: | IEEE Micro. 41:80-86 |
| ISSN: | 1937-4143 0272-1732 |
| Popis: | Cryogenic computing can achieve high performance and power efficiency by dramatically reducing the device’s leakage power and wire resistance at low temperatures. Recent advances in cryogenic computing focus on developing cryogenic-optimal cache and memory devices to overcome memory capacity, latency, and power walls. However, little research has been conducted to develop a cryogenic-optimal core architecture even with its high potentials in performance, power, and area efficiency. In this article, we first develop CryoCore-Model, a cryogenic processor modeling framework that can accurately estimate the maximum clock frequency of processor models running at 77 K. Next, driven by the modeling tool, we design CryoCore, a 77 K-optimal core microarchitecture to maximize the core’s performance and area efficiency while minimizing the cooling cost. The proposed cryogenic processor architecture, in this article, achieves the large performance improvement and power reduction and, thus, contributes to the future of high-performance and power-efficient computer systems. |
| Databáze: | OpenAIRE |
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