Performance and Variations Induced by Single Interface Trap of Nanowire FETs at 7-nm Node
| Autor: | Jun-Sik Yoon, Taiuk Rim, Kihyun Kim, Chang-Ki Baek |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Materials science business.industry Nanowire Oxide Electrical engineering 02 engineering and technology Dielectric RC time constant 021001 nanoscience & nanotechnology 01 natural sciences Molecular physics Electronic Optical and Magnetic Materials Ion chemistry.chemical_compound chemistry Logic gate 0103 physical sciences Electrical and Electronic Engineering 0210 nano-technology Electronic band structure business Leakage (electronics) |
| Zdroj: | IEEE Transactions on Electron Devices. 64:339-345 |
| ISSN: | 1557-9646 0018-9383 |
| Popis: | DC/AC performance and the variations due to single interface trap of the nanowire (NW) FETs were investigated in the 7-nm technology node using fully calibrated TCAD simulation. Shorter junction gradient and greater diameter reduced RC delay without short channel degradations. Spacer with smaller dielectric constants decreased parasitic and gate capacitances with a slight decrease of ON-state currents, thus minimizing RC delay. Interface traps for the variability analysis were ${P}_{b0}$ , ${P}_{b1}$ , and fixed oxide charges at the Si/SiO2 interface. ${P}_{b0}$ negligibly affected dc variations but ${P}_{b1}$ at the drain underlap regions increased gate-induced drain leakage currents, which induced greater OFF-state current variations. Fixed oxide charges, especially at the middle of the channel regions, shifted drain currents toward left by bending the energy band downward locally near the single interface trap. To maximize the performance as well as to minimize the variations induced by the interface traps, careful surface treatment for the drain underlap regions and adaptation of vertical NW structure are needed while maintaining fine short channel characteristics. |
| Databáze: | OpenAIRE |
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