| Autor: |
Pragati K. Tiwary, Rob A. Rutenbar, Saurabh K. Tiwary |
| Rok vydání: |
2006 |
| Předmět: |
|
| Zdroj: |
DAC |
| DOI: |
10.1145/1146909.1146921 |
| Popis: |
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulator-in-a-loop approach. The solutions on this pareto front combined with efficient Monte Carlo approximation ideas are then used to compute the yield-aware pareto fronts. We show experimental results for both the nominal and yield-aware pareto fronts for power and phase noise for a voltage controlled oscillator (VCO) circuit. The presented methodology computes yield-aware pareto fronts in approximately 5-6 times the time required for a single circuit synthesis run and is thus practically efficient. We also show applications of yield-aware paretos to find the optimal VCO circuit to meet the system level specifications of a phase locked loop. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
|
