Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition
| Autor: | Dan Mocuta, E. Chiu, Nadine Collaert, Roger Loo, Robert Langer, A. De Keersgieter, Paola Favia, Liesbeth Witters, Hiroaki Arimura, Frank Holsteyns, Farid Sebaai, Kathy Barla, E. Vancoille, Andreas Schulze, Tom Schram, V. De Heyn, Steven Bilodeau, Andriy Hikavyy, Peter Storck, Jerome Mitard, A. Opdebeeck, Katia Devriendt, Emanuel I. Cooper, Christa Vrancken, Ruben R. Lieten, Geert Eneman, Kurt Wostyn, Alexey Milenin, Niamh Waldron |
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| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Materials science business.industry Nanowire chemistry.chemical_element Germanium Nanotechnology 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences Subthreshold slope Electronic Optical and Magnetic Materials PMOS logic Silicon-germanium Gallium arsenide chemistry.chemical_compound chemistry 0103 physical sciences Optoelectronics Electrical and Electronic Engineering 0210 nano-technology business Metal gate Leakage (electronics) |
| Zdroj: | IEEE Transactions on Electron Devices. 64:4587-4593 |
| ISSN: | 1557-9646 0018-9383 |
| DOI: | 10.1109/ted.2017.2756671 |
| Popis: | Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single horizontal Ge nanowire (NW) devices are demonstrated, the process flow described in this paper can be adjusted to make vertically stacked horizontal Ge NWs to increase the drive per footprint. The demonstrated short-channel devices have round Ge NWs with 9-nm diameter and are the Ge GAA devices with the smallest channel and gate dimensions ( $L_{G}= 40$ nm) published to date. Electrostatics and off-state leakage are maintained down to the shortest gate lengths studied, showing drain-induced barrier lowering of 30 mV/V and sub-20 nA/ $\mu \text{m}~I_{\mathrm{\scriptscriptstyle off}}$ at $V_{\mathrm {{\text {DD}}}}= -0.5$ V and $L_{G}= 40$ nm. The short-channel device subthreshold slope SS and performance can be further improved by use of high-pressure annealing in hydrogen, yielding the best SSLIN and SSSAT of 71 and 76 mV/dec reported so far for any $L_{G}= 40$ -nm Ge pMOS channel device. |
| Databáze: | OpenAIRE |
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