Machine Learning for Congestion Management and Routability Prediction within FPGA Placement
| Autor: | Shawki Areibi, Abeer Al-Hyari, Timothy Martin, Jeremy Foxcroft, Gary Grewal, David Noel, Hannah Szentimrey |
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| Rok vydání: | 2020 |
| Předmět: |
Router
Computer science business.industry 0211 other engineering and technologies 02 engineering and technology Congestion management Machine learning computer.software_genre Computer Graphics and Computer-Aided Design Convolutional neural network 020202 computer hardware & architecture Computer Science Applications Linear regression 0202 electrical engineering electronic engineering information engineering Artificial intelligence Electrical and Electronic Engineering Field-programmable gate array business computer Design closure 021106 design practice & management |
| Zdroj: | ACM Transactions on Design Automation of Electronic Systems. 25:1-25 |
| ISSN: | 1557-7309 1084-4309 |
| DOI: | 10.1145/3373269 |
| Popis: | Placement for Field Programmable Gate Arrays (FPGAs) is one of the most important but time-consuming steps for achieving design closure. This article proposes the integration of three unique machine learning models into the state-of-the-art analytic placement tool GPlace3.0 with the aim of significantly reducing placement runtimes. The first model, MLCong, is based on linear regression and replaces the computationally expensive global router currently used in GPlace3.0 to estimate switch-level congestion. The second model, DLManage, is a convolutional encoder-decoder that uses heat maps based on the switch-level congestion estimates produced by MLCong to dynamically determine the amount of inflation to apply to each switch to resolve congestion. The third model, DLRoute, is a convolutional neural network that uses the previous heat maps to predict whether or not a placement solution is routable. Once a placement solution is determined to be routable, further optimization may be avoided, leading to improved runtimes. Experimental results obtained using 372 benchmarks provided by Xilinx Inc. show that when all three models are integrated into GPlace3.0, placement runtimes decrease by an average of 48%. |
| Databáze: | OpenAIRE |
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