Immersion lithography scanner readiness for volume manufacturing on 450mm substrates: AP/DFM: Advanced patterning/design for manufacturability
| Autor: | Jasper P. Munson, Christopher R. Carr, Russell A. Black |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Engineering
business.industry Extreme ultraviolet lithography 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences Die (integrated circuit) Design for manufacturability law.invention 010309 optics Cost reduction Resist law 0103 physical sciences Hardware_INTEGRATEDCIRCUITS Electronic engineering Photolithography 0210 nano-technology business Lithography Immersion lithography |
| Zdroj: | 2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC). |
| DOI: | 10.1109/asmc.2016.7491082 |
| Popis: | The semiconductor industry finds itself at a crossroad with the question of how to continue to drive Moore's law. The industry is exploring many avenues to drive transistor scaling as well as reduction in cost for the future nodes. Some of the popular topics for patterning advancement include EUV, DSA, EBeam direct write, and Nano-Imprint. This paper will focus on the reduction in cost brought about by the scaling of the wafer size, and demonstrate where the current 450mm equipment compares to current 300mm toolsets as well as the N10 and N7 technology roadmaps. The semiconductor industry currently utilizes 300mm substrates for volume manufacturing around the world. The Global 450mm Consortium (G450C) was created to develop and evaluate a manufacturing tool set for 450mm substrates. In 2015 Nikon released the NSR-S650D scanner for 193nm immersion lithography on 450mm substrates. The Photolithography cluster at G450C is a fully integrated 450mm cell including a SCREEN Sokudo Duo DT-4000 track attached to the Nikon NSR-S650D scanner. The equipment was installed in Q1-Q2 2015 and was qualified and accepted by the fall of 2015. This paper will demonstrate data from the time of acceptance as well as recent data that has been collected after several continuous improvement plan (CIP) implementations. The current method for transistor density scaling is multi-patterning. The key metric to evaluate lithography capability for multi-patterning is edge placement error. Edge placement error (EPE) is the cumulative sum of all error in the lithography process [1]. Critical dimension uniformity (CDU) and overlay have the largest impact on EPE [2] and will be used to evaluate the lithography cell at G450C. This paper will show the CDU and overlay performance at the time of acceptance as well as current data. The performance of the NSR-S650D will be compared to the current 300mm platforms as well as the technology requirements for N10 and N7. Multi-patterning enables transistor scaling; however it comes with increased wafer cost. 450mm substrates increase the surface area over 300mm by a factor of 2.25. For most fab equipment the increased surface area directly correlates to more die per wafer pass and more die out. To drive cost reduction in lithography remains the largest challenge; lithography tools scan exposure shots individually and the throughput is always scan limited. This paper will demonstrate how the tool currently performs for throughput and will discuss some software optimizations to increase wafers per hour (WPH). A comparison of 450mm WPH to current 300mm toolsets will also be evaluated. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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