A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
| Autor: | Shyh-Jye Jou, Chung-Ping Huang, Yung-Shin Kao, Ya-Ping Wu, Chien-Yu Lu, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Ming-Hsien Tu, Ching-Te Chuang |
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| Rok vydání: | 2015 |
| Předmět: | |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:958-962 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/tvlsi.2014.2318518 |
| Popis: | This brief presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with independent single-ended read bitline and write bitline (WBL) and cross-point data-aware write structure to facilitate robust subthreshold operation and bit-interleaving architecture for enhanced soft error immunity. The design employs a variation-tolerant line-up write-assist scheme where the timing of area-efficient boosted write wordline and negative WBL are aligned and triggered/initiated by the same low-going global WBL to maximize the write-ability enhancement. A 72-kb test chip is implemented in United Microelectronics Corp. 40-nm low-power (40LP) CMOS. Full functionality is achieved for V $_{\mathrm {DD}}$ ranging from 1.5 to 0.32 V without redundancy. The measured maximum operation frequency is 260 MHz (450 kHz) at 1.1 V (0.32 V) and 25 °C. At 0.325 V and 25 °C, the chip operates at 600 kHz with 5.78 $\mu $ W total power and 4.69 $\mu $ W leakage power, offering $2\times $ frequency improvement compared with 300 kHz of our previous 72-kb 9T subthreshold SRAM design in the same 40LP technology. The energy efficiency (power/frequency/IO) at 0.325 V and 25 °C is 0.267 pJ/bit, a 23.7% improvement over the 0.350 pJ/bit of our previous design. |
| Databáze: | OpenAIRE |
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