HSRDN: High‐Speed Router Design for Various NoC Topologies
| Autor: | M. N. Giri Prasad, A.R. Reddy, E. Lakshmi Prasad |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
Router
Computer science business.industry Applied Mathematics 020206 networking & telecommunications Cryptography 02 engineering and technology Integrated circuit design Network topology Network on a chip Traffic congestion 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Polygon mesh Electrical and Electronic Engineering Latency (engineering) business Computer network |
| Zdroj: | Chinese Journal of Electronics. 29:281-290 |
| ISSN: | 2075-5597 1022-4653 |
| DOI: | 10.1049/cje.2020.01.005 |
| Popis: | High-speed router design for network on chip (HSRDN) is proposed for controlling the traffic congestion and deadlocks. Diagonal based nearest-path routing algorithm for NoC (DNRAN) can mitigate the effect of latency by opting for the nearest-path to reach the destination in a network and HSRDN is part of DNRAN. When we analyze the performance of DNRAN for all proposed topologies, nearly 50% better in terms of latency reduction and high throughput over existing router architectures. The proposed topologies (2D-mesh, 2D-Star mesh over regional mesh (SMoRM), 3D-mesh, and 3D-torus) are tested with various applications, viz, audio, video and so on. Here, we also tested with cryptography application for DNRAN. When we analyzed the performance of experimental results, exclusively in 2D-SMoRM nearly 0.6 times latency get reduced, area expanded by 0.25 and 0.33 times throughput increase in 2D-SMoRM compared with 3D-mesh and 3D-torus. Therefore, DNRAN showed an exclusive performance in 2D-SMoRM compared with other two topologies. |
| Databáze: | OpenAIRE |
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