A Novel Low Power Dynamic Memory Architecture Using Single Supply 3T Gain Cell
| Autor: | Gadham Mamatha, S. Rajendar, Malladhi Nagarjuna |
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| Rok vydání: | 2017 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Computer science Sense amplifier 020208 electrical & electronic engineering Real-time computing Registered memory Semiconductor memory 02 engineering and technology Memory controller 020202 computer hardware & architecture Universal memory Memory architecture 0202 electrical engineering electronic engineering information engineering Interleaved memory Electronic engineering Memory refresh |
| Zdroj: | 2017 IEEE 7th International Advance Computing Conference (IACC). |
| DOI: | 10.1109/iacc.2017.0097 |
| Popis: | Design of memory consists of two different approaches namely, static random access memory (SRAM) and dynamic random access memory (DRAM). Traditionally SRAM has been used to design memory. The major problem to design a memory using SRAM is area, power and delay. The memories designed with SRAM will result in high power, high delay and consumes more area. To overcome this problem, a DRAM cell is designed witch results in low power, low area and low delay. There are certain disadvantages with these two designs, and to overcome limitations a new gain cell is designed in this paper. A 2Kb dynamic memory architecture has been designed using the proposed modified 3T gain cell. An architecture is designed with features of high speed, low power, and low delay. The dyanmic memory architecture is implemented using Cadence Analog Design Environment. The proposed and conventional dynamic memory architectures were compared in terms of power and delay for variable supply voltages and temperatures. |
| Databáze: | OpenAIRE |
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