| Autor: |
Yevhenii V. Kuts, Timofii V. Yakushkin, Serhii I. Yatsenko, Volodymyr Voytenko, Roman D. Yershov, Viacheslav Gordienko |
| Rok vydání: |
2021 |
| Předmět: |
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| Zdroj: |
IEEE EUROCON 2021 - 19th International Conference on Smart Technologies. |
| DOI: |
10.1109/eurocon52738.2021.9535641 |
| Popis: |
Video graphics array (VGA) is a still commonly used display interface standard in embedded systems. Due to traditional microprocessor cannot provide timings for high-resolution VGA interface it is often implemented as a part of FPGA-based image processing flow. The main problem is that FPGA-based project need to be covered with an adequate set of tests which allow verifying the functionality the whole image processing flow even without availability of real FPGA IC and/or monitor. This, in turn, remains difficult without the visualization of resulted image. A hardware verification technique of digital VGA generator synthesized on the FPGA basis that uses of an unsynthesized subset of the System Verilog language has been proposed in this paper. A full-featured object-oriented package for BMP-files processing is developed and its integration inside the FPGA-project is shown. Moreover, the synthesizable part of design has been hardware tested on the DE10-Lite board. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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