Optimizing OpenCL applications on Xilinx FPGA
| Autor: | Ronan Keryell, Jim Wu, Hervé Ratigner, Jeff Fifield, Henry E. Styles |
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| Rok vydání: | 2016 |
| Předmět: |
060201 languages & linguistics
business.industry Computer science Interface (computing) 06 humanities and the arts 02 engineering and technology Chip Reconfigurable computing Imperative programming Computer architecture Gate array Embedded system 0602 languages and literature 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Hardware_ARITHMETICANDLOGICSTRUCTURES business Field-programmable gate array Digital signal processing FPGA prototype |
| Zdroj: | IWOCL |
| Popis: | In this presentation we focus on current Xilinx FPGA (Field-Programmable Gate Array) platforms with the SDAccel OpenCL environment. FPGA have the unique feature of a reconfigurable architecture by opposition to CPU, GPU or DSP which have a fixed architecture and are only programmable. For example the elementary functions in an FPGA can be configured according to an addressable memory, as such the interconnection among them, the internal memory organization, but also even the ultra high-speed input/output of the chip to interface with the outside world. This fine grain configurability allows high performance and power efficiency. We introduce the architecture of modern FPGA with their main building blocks and how functional operations can be expressed. The translation of imperative languages down to the hardware level is done through High-Level Synthesis. It can be done in several ways with different time/surface trade-off, for example by playing on parallelism and pipelining. |
| Databáze: | OpenAIRE |
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