A 2.6mm2 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applications
| Autor: | Hsiao-En Chen, Ping Chao, Min-Hao Chiu, Hue-Min Lin, Chen Yi-Chang, Hsiu-Yi Lin, Chih-Wen Yang, Yung-Chang Chang, Shun-Hsiang Chuang, Meng-Jye Hu, Chi-cheng Ju, Chia-Yun Cheng, Fu-Chun Yeh, Che-Hong Chen, Peng Hsuan-Wen, Sheng-Jen Wang, Yenchieh Huang, Chun-Chia Chen, Chih-Ming Wang, Ming-Long Wu, Kao Chia-Hung, Tsu-Ming Liu, Chia-Lin Ho |
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| Rok vydání: | 2016 |
| Předmět: |
Pixel
business.industry Computer science 020208 electrical & electronic engineering Video decoder 02 engineering and technology Chip CMOS Embedded system 0202 electrical engineering electronic engineering information engineering Single-core Android (operating system) business Computer hardware Decoding methods Efficient energy use |
| Zdroj: | ESSCIRC |
| DOI: | 10.1109/esscirc.2016.7598254 |
| Popis: | A lower power and area efficient VP9 and multi-standard video decoder chip is first-reported for Android 4K TV. It supports prevalent MPEG-x, VP-x, RMx, WMV-x and H.26x series video standards in a single chip. Three high-throughput techniques, look-ahead re-mapping, early stage pipeline and dynamic-scheduled bus translation, are proposed. They cuts the processing times by 51.2% compared to the state-of-the-art design [4]. Moreover, two area-efficient techniques, hybrid backward probability update and tile-to-raster scan ordering, are designed to reduce the internal memory size by 10%. A mass-production chip is fabricated in a 28nm CMOS technology with an energy efficiency of 0.19nJ/pixel and an area of 2.6mm2. Compared to the dual-core decoder design [4], this work achieves the identical performance (4K@60fps) with single core which cut one-half of chip area. |
| Databáze: | OpenAIRE |
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