90nm low leakage SoC design techniques for wireless applications

Autor:	Mark Streeter, Julie Dong, Franck Dahan, H. Clasen, Hugh Mair, C. Raibaut, B. Pitts, L. Bouetel, Joel Blasquez, Philippe Royannez, David B. Scott, G. Semino, Uming Ko, Mike Wagner
Rok vydání:	2005
Předmět:	Engineering Hardware_MEMORYSTRUCTURES Power gating business.industry Transistor Hardware_PERFORMANCEANDRELIABILITY law.invention CMOS Hardware_GENERAL law Hardware_INTEGRATEDCIRCUITS Electronic engineering Wireless System on a chip business Scaling Hardware_LOGICDESIGN Leakage (electronics) Voltage
Zdroj:	ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
DOI:	10.1109/isscc.2005.1493907
Popis:	The new generation of multimedia-application processors requires a drastic leakage reduction to bring the standby current to 50/spl mu/A. An efficient set of leakage reduction techniques, including power gating, memory retention, voltage scaling, and dual V/sub t/, is employed on a 50M transistor, 80mm/sup 2/ IC, fabricated in a 90nm CMOS technology, resulting in a 40/spl times/ leakage reduction.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::78645f69da097f9a53c7cf10e69e512b https://doi.org/10.1109/isscc.2005.1493907 Zobrazit plný text záznamu