Design and performance of multistage GaAs dynamic logic
| Autor: | F. Hoeg, S.I. Long, Uddalak Bhattacharya |
|---|---|
| Rok vydání: | 1995 |
| Předmět: |
Engineering
Adder Pass transistor logic business.industry Electrical engineering Logic family Hardware_PERFORMANCEANDRELIABILITY Logic synthesis Logic gate Hardware_INTEGRATEDCIRCUITS Electronic engineering MESFET Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering business Dynamic logic (digital electronics) Hardware_LOGICDESIGN Asynchronous circuit |
| Zdroj: | IEEE Journal of Solid-State Circuits. 30:580-585 |
| ISSN: | 0018-9200 |
| Popis: | GaAs Two-Phase Dynamic FET Logic (TDFL) circuits are capable of extremely low power dissipation (20 nW/MHz/gate), high speed (1 GHz), and are compatible with static GaAs logic families. This paper demonstrates that TDFL can be modified to execute two or three stages of logic in one clock phase. This extension provides extremely high functional complexity per gate that can be used to reduce power dissipation, reduce latency, and increase circuit density in both sequential and computationally-oriented applications. The performance of these gates was demonstrated by E/D MESFET IC test circuits fabricated by a digital IC foundry. A one clock cycle, 8-b carry-lookahead adder operated at 350 MHz with only 1.1 mW of power dissipation. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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