3D-Sorter: 3D Design of a Resource-Aware Hardware Sorter for Edge Computing Platforms Under Area and Energy Consumption Constraints
| Autor: | Zahra Kazemi, Amin Norollah, David Hely |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
Sorting algorithm
business.industry Computer science 020208 electrical & electronic engineering Sorting 02 engineering and technology Energy consumption 020202 computer hardware & architecture Partial sorting Dimension (vector space) Lookup table 0202 electrical engineering electronic engineering information engineering Enhanced Data Rates for GSM Evolution business Edge computing Computer hardware |
| Zdroj: | ISVLSI |
| DOI: | 10.1109/isvlsi49217.2020.00018 |
| Popis: | In this paper, we proposed a 3-dimensional hardware sorting architecture (3D-Sorter), based on MultiDimensional Sorting Algorithm (MDSA). the proposed architecture transforms a sequence of input records into a 3-dimensional matrix. Records of every dimension are sorted in several MDSA phases, using partial sorting methods. Our synthesis results, provided by Xilinx Vivado indicate that the 3D-Sorter design decreases the number of Look-Up Tables (LUT) and registers by 54% and 42.7%, compared to the state-of-the-art hardware sorter. Also, the power consumption is reduced by 48.15% on average. The results show that the proposed architecture is a remarkable power/area saving for edge components. |
| Databáze: | OpenAIRE |
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