A 600 MHz single-chip multiprocessor with 4.8 GB/s internal shared pipelined bus and 512 kB internal memory

Autor:	S. Kaneko, K. Sawai, N. Masui, K. Ishimi, T. Itou, M. Satou, H. Kondo, N. Okumura, Y. Takata, H. Takata, M. Sakugawa, T. Higuchi, S. Ohtani, K. Sakamoto, N. Ishikawa, M. Nakajima, S. Iwata, K. Hayase, S. Nakano, S. Nakazawa, O. Tomisawa, T. Shimizu
Rok vydání:	2003
Zdroj:	2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
DOI:	10.1109/isscc.2003.1234290
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::779230422ba96363b7716a1e8189f7fe https://doi.org/10.1109/isscc.2003.1234290 Zobrazit plný text záznamu