Clock generation for a 32nm server processor with scalable cores

Autor:	Edward Helder, Shenggao Li, Roan M. Nicholson, Vivian Jia, Ashwin Krishnakumar
Rok vydání:	2011
Předmět:	Phase-locked loop CMOS business.industry Computer science Embedded system Scalability business Inductor Synchronization Jitter
Zdroj:	ISSCC
DOI:	10.1109/isscc.2011.5746229
Popis:	Within a given power envelope, the performance of a multi-core enterprise processor is greatly affected by inter-core (including I/O) data throughput and data transport latency. This paper presents the implementation of a clock system targeting low-power low-skew high-data throughput and low latency for a next-generation Xeon® server processor [1,2] with scalable cores in a 32nm 9-metal digital CMOS process.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::7785459fb0673b01c3aee8797fa44508 https://doi.org/10.1109/isscc.2011.5746229 Zobrazit plný text záznamu