A Reliability Overview of Intel’s 10+ Logic Technology
| Autor: | Benjamin J. Orr, Nathan Jack, C. Auth, A. Schmitz, Tony Acosta, Steven S. Poon, Che-Yun Lin, Abdur Rahman, C. AnDyke, Rahim Kasim, K. Downes, G. McPherson, Sunny Chugh, Madhavan Atul, D. Nminibapiel, Adam Neale, K. Sethi, Seung Hwan Lee, S. Ramey, Tanmoy Pramanik, Michael L. Hattendorf, Emre Armagan, J. Palmer, Subhash M. Joshi, Ian R. Post, C. M. Pelto, P. Nayak, Yeoh Andrew W, G. Martin, Gerald S. Leatherman, H. Wu, N. Seifert, A. Lowrie, R. Grover, H. Mao |
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| Rok vydání: | 2020 |
| Předmět: |
Computer science
business.industry Electrical engineering Strained silicon Hardware_PERFORMANCEANDRELIABILITY Certification Third generation law.invention Capacitor Reliability (semiconductor) Hardware_GENERAL law Hardware_INTEGRATEDCIRCUITS Isolation (database systems) Routing (electronic design automation) Metal gate business Hardware_LOGICDESIGN |
| Zdroj: | IRPS |
| Popis: | We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high-k metal gate, multi-Vt options, contact over active gate, single-gate isolation, 14 metal layers, low-k inter-layer dielectric, multi-plate metal-insulator-metal capacitors, two thick-metal routing layers for low-resistance power routing, and lead-free packaging. The technology meets all relevant reliability metrics for certification. |
| Databáze: | OpenAIRE |
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