Two gates are better than one [double-gate MOSFET process]
| Autor: | Kathryn W. Guarini, Guy M. Cohen, H.J. Hovel, J. Benedict, C. Cabral, K. Petrarca, Diane C. Boyd, Raymond M. Sicina, J.H. Yoon, J. Newbury, P. Kozlowski, Paul M. Solomon, Hon-Sum Philip Wong, Christopher P. D'Emic, A. Krasnoperova, M. Ronay, K.K. Chan, V. Ku, O. Dokumaci, Christian Lavoie, Inna V. Babich, J.J. Bucchignano, E.C. Jones, J. Treichler, Y. Zhang |
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| Rok vydání: | 2003 |
| Předmět: |
Very-large-scale integration
Engineering business.industry Transistor Electrical engineering NOR logic Hardware_PERFORMANCEANDRELIABILITY Electronic Optical and Magnetic Materials law.invention CMOS law Gate oxide MOSFET Hardware_INTEGRATEDCIRCUITS Optoelectronics Electrical and Electronic Engineering business Instrumentation AND gate NMOS logic Hardware_LOGICDESIGN |
| Zdroj: | IEEE Circuits and Devices Magazine. 19:48-62 |
| ISSN: | 8755-3996 |
| Popis: | A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of the back-gate layer after the S/D structure is in place. This allows coupling the silicon thickness control inherent in a planar, unpatterned layer with VLSI self-alignment techniques and also gives independently controlled front and back gates. The demanding structure led to process innovations primarily in front-end CMP, where planarity within 5 nm was achieved on an 8-in diameter wafer as well as in silicided silicon source/drain sidewalls, with minimal encroachment of the silicide. Double-gate FET (DGFET) operation is demonstrated, with good transport at both interfaces. Dense circuit layouts are achieved with multifinger devices, and logic inverters with back-gate-controlled load current as well as NOR logic using the two gates of a single transistor as inputs are demonstrated. |
| Databáze: | OpenAIRE |
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