All-Digital Duty-Cycle Corrector With a Wide Duty Correction Range for DRAM Applications
| Autor: | In-Chul Hwang, Chan-Hui Jeong, Soo-Won Kim, Ammar Abdullah, Young-Jae Min |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Very-large-scale integration
business.industry Computer science 020208 electrical & electronic engineering Detector Electrical engineering Operating frequency 02 engineering and technology Dissipation Chip 020202 computer hardware & architecture Hardware and Architecture 0202 electrical engineering electronic engineering information engineering Electronic engineering Digital comparator Electrical and Electronic Engineering business Double data rate Software Dram Jitter |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24:363-367 |
| ISSN: | 1557-9999 1063-8210 |
| Popis: | An all-digital duty-cycle corrector with a wide duty correction range and fast correction time is hereby presented. The proposed corrector uses a 1-bit digital duty-cycle detector with a time-to-digital converter, and it achieves a duty correction range between 10% and 90% with a low pressure, volume, and temperature variation. The test chip was fabricated using a 0.13- $\mu $ m CMOS process, and it occupies an area of 0.059 mm $^{2}$ . The correction cycle is a 14 cycles and the duty-cycle error is below ±1.4%. At an operating frequency of 1 GHz, the power dissipation and peak-to-peak jitter are measured at 5.6 mW and 20.5 ps, respectively. |
| Databáze: | OpenAIRE |
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