| Autor: |
Ravi Pokhrel, Yil-Hak Lee, Won-Hyun Lee, Su-Han Woo, Mark Scalisi, Yu Hua Kao, Luis Gomez, Mark Lefebvre, Jonathan D Prange, Kirk Thompson |
| Rok vydání: |
2018 |
| Zdroj: |
ECS Meeting Abstracts. :1137-1137 |
| ISSN: |
2151-2043 |
| DOI: |
10.1149/ma2018-02/33/1137 |
| Popis: |
The micro-electronics packaging industry is seeking new Cu electroplating products to achieve improved I/O density in chips and to enable a variety of packaging architectures. Solder-capped copper pillars are currently used as interconnects in advanced chip packaging. The technology trend is to utilize finer pitch size and smaller Cu pillar interconnects, thereby categorizing electroplated Cu pillars as standard pillars (20-75 µm feature sizes) and µ-pillars ( |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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