Bit-serial CORDIC: Architecture and implementation improvements

Autor:	Peter M. Nilsson, Johan Lofgren
Rok vydání:	2010
Předmět:	Adder business.industry Computer science Hardware description language Control unit Parallel computing Reduction (complexity) Logic gate VHDL Hardware_ARITHMETICANDLOGICSTRUCTURES CORDIC business Throughput (business) computer Computer hardware computer.programming_language
Zdroj:	2010 53rd IEEE International Midwest Symposium on Circuits and Systems.
DOI:	10.1109/mwscas.2010.5548562
Popis:	This paper presents a new and improved bit-serial CORDIC architecture. A detailed description of the bit-serial implementation and its Control Unit is presented. It is shown that the improvement is due to a reduction of registers in the implementation and is made possible by ensuring that the angular path is calculated prior to the corresponding vector paths. In addition, the improved architecture is implemented in VHDL and synthesized for a UMC 130 nm technology. With the chosen parameters, a word length of 12 bits and 8 stages in the CORDIC, it is shown that the improved architecture is 20 % smaller and consumes 26 % less power.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::7621fba83f5eb54b0a3884bc62b03a03 https://doi.org/10.1109/mwscas.2010.5548562 Zobrazit plný text záznamu