High Resolution Digital Pulse Width Modulated Signal Scheme on FPGA
| Autor: | K. S Riyas, Sheaba Thomas |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
021110 strategic
defence & security studies Computer science 020208 electrical & electronic engineering 0211 other engineering and technologies 02 engineering and technology Digital clock manager Converters Signal Power (physics) Control system Lookup table 0202 electrical engineering electronic engineering information engineering Electronic engineering Field-programmable gate array Pulse-width modulation |
| Zdroj: | 2020 Third International Conference on Advances in Electronics, Computers and Communications (ICAECC). |
| Popis: | In recent years, digital pulse width modulator (DPWM) has been widely used in the fields of electronic engineering, such as power converters, digital radar systems, control systems etc. High-resolution DPWM signal is simulated on ISE (Integrated Synthesis Environment) Design Suite 14.5 using two different approaches and a modified method. The first approach is based on Digital Clock Manager (DCM) module, which provides more stability than the RS latch utilized in previous work. As for the second method, look-up-table (LUT) is employed as the basic resources to construct high resolution DPWM signal. This can be easily implemented on low-cost FPGA devices because of the significantly simplified structure. The resolutions of two approaches can reach upto 625ps and 500ps respectively. In modified method, the resolution of DPWM signal can reach upto 1250ps. |
| Databáze: | OpenAIRE |
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