A 35-dBm OIP3 CMOS Constant Bandwidth PGA With Extended Input Range and Improved Common-Mode Rejection
| Autor: | Xiaoying Deng, Jianhui Wu, Chunfeng Bai, Chao Chen |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Physics
business.industry 020208 electrical & electronic engineering Bandwidth (signal processing) Electrical engineering Linearity 020206 networking & telecommunications 02 engineering and technology law.invention Capacitor Programmable-gain amplifier Common-mode rejection ratio Parasitic capacitance CMOS law Current conveyor Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electrical and Electronic Engineering business |
| Zdroj: | IEEE Transactions on Circuits and Systems II: Express Briefs. 64:922-926 |
| ISSN: | 1558-3791 1549-7747 |
| DOI: | 10.1109/tcsii.2016.2641004 |
| Popis: | An improved CMOS second generation current conveyor with adaptive control circuit (ACC) is proposed, and is used to build a highly linear transconductance–transimpedance programmable gain amplifier (PGA). This PGA is fabricated in a 0.18- $\mu \text{m}$ CMOS technology and draws a 0.58-mA current from a supply of 1.8 V. It achieves a 0–14-dB-gain range within a roughly constant bandwidth of 30 MHz when driving a capacitor load of 2 pF. Enhanced linearity, extended input range, and improved common-mode rejection are achieved due to the employ of the proposed ACC. In addition, gain peaking is less prone to appear as the proposed ACC contributes a significant reduction in ${X}$ terminal parasitic capacitance. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|