Skew-aware polarity assignment in clock tree

Autor:	Po-Yuan Chen, TingTing Hwang, Kuan-Hsien Ho
Rok vydání:	2009
Předmět:	Computer science Real-time computing Clock gating Digital clock manager Clock skew Computer Graphics and Computer-Aided Design Timing failure Computer Science Applications Clock network Clock angle problem Clock domain crossing Electrical and Electronic Engineering Algorithm CPU multiplier
Zdroj:	ACM Transactions on Design Automation of Electronic Systems. 14:1-17
ISSN:	1557-7309 1084-4309
DOI:	10.1145/1497561.1497574
Popis:	In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in previous work. Although peak current and power/ground noises are minimized by signal polarities assignment, an assignment without timing information may increase the clock skew significantly. As a result, a timing-aware signal polarities assigning technique is necessary. In this article, we propose a novel signal polarities assigning technique which can not only reduce peak current and power/ground noises simultaneously but also render the clock skew in control. The experimental result shows that the clock skew produced by our algorithm is 94% of original clock skew in average while the clock skews produced by three algorithms (Partition, MST, Matching) in the absence of post clock tuning steps in the previous work are 235%, 272%, and 283%, respectively. Moreover, our algorithm is as efficient as the three algorithms of the previous work in reducing peak current and power/ground noises.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::74f034dc5a8d968a8bf4185e29cb425b https://doi.org/10.1145/1497561.1497574 Zobrazit plný text záznamu