Schottky collector I/sup 2/L
| Autor: | R.P. Mertens, S.C. Blackstone |
|---|---|
| Rok vydání: | 1977 |
| Předmět: |
Physics
Pass transistor logic business.industry Schottky barrier Transistor Electrical engineering Logic family Resistor–transistor logic law.invention Integrated injection logic Sphere packing law Hardware_INTEGRATEDCIRCUITS Optoelectronics Beta (velocity) Electrical and Electronic Engineering business Hardware_LOGICDESIGN |
| Zdroj: | IEEE Journal of Solid-State Circuits. 12:270-275 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.1977.1050890 |
| Popis: | A new I/SUP 2/L gate which promises increased packing density and increased speed is discussed. It incorporates the use of a Schottky contact as the collector of the vertical switching transistor of an I/SUP 2/L gate. Calculations and experiments show that the problems associated with this structure (low downward beta) can be controlled by limiting both the fan-out and the fan-in. Delays of less than 10 ns have been measured using a 10-/spl mu/m technology and a 6-/spl mu/m-thick epi. A divide-by-two circuit with a maximum toggle frequency of 12.5 MHz has been built. The additional fan-in limitation of the logic is described. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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