A Hypothesis Verification Method Using Regression Tree for Semiconductor Yield Analysis

Autor:	Hidetaka Tsuda, Kazuo Hashimoto, Hidehiro Shirai, Masahiro Terabe, Ayumi Shinohara
Rok vydání:	2011
Předmět:	Regression tree analysis Yield (finance) Statistics Hypothesis verification Decision tree Econometrics Electrical and Electronic Engineering Industrial and Manufacturing Engineering Factor regression model Logistic model tree Mathematics
Zdroj:	IEEJ Transactions on Industry Applications. 131:1232-1239
ISSN:	1348-8163 0913-6339
DOI:	10.1541/ieejias.131.1232
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::74b0d92b519c15cf5a34ee90c92258eb https://doi.org/10.1541/ieejias.131.1232 Zobrazit plný text záznamu