Numerical analysis of hardware architecture for header compression and packet aggregation on wireless networks
| Autor: | Sangkil Jung, Sangjin Hong |
|---|---|
| Rok vydání: | 2009 |
| Předmět: |
Hardware architecture
Wireless mesh network Computer Networks and Communications Wireless network Computer science Robust Header Compression Real-time computing Mesh networking Parallel computing Packet aggregation SystemC Electrical and Electronic Engineering computer Processing delay Information Systems computer.programming_language |
| Zdroj: | Wireless Networks. 16:1477-1491 |
| ISSN: | 1572-8196 1022-0038 |
| DOI: | 10.1007/s11276-009-0215-9 |
| Popis: | This paper proposes a numerical analysis model to predict the processing delay of a hardware architecture for robust header compression and packet aggregation on wireless mesh networks. The analysis model is composed of a series of queue systems such as G/M/1, M [K]/M/1, M/M/1, and M/M/� that are one-to-one mapped into the constructed hardware components to characterize the concurrent operations and interactional relationship between encoding and decoding paths. Based on the co-simulation method which integrates NS-2 and SystemC, we show the analysis model properly approximates the processing delay of the hardware architecture. Additionally, the variation of processing delay occurring when a part of hardware components are differently configured is suitably characterized by the proposed model, and the overall mesh network behaviors is predicted by applying the numerical results into NS-2 simulations. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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