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Hardware accelerators as co-processors are emerging as a powerful solution to computationally intensive problems. A standard desktop PC or cluster node can be augmented with additional hardware dedicated to providing substantially increased performance for particular applications. Previous efforts have shown that FPGA-based hardware accelerators can offer order-of-magnitude greater performance than conventional CPUs, providing the target algorithm performs a large number of operations per data point. FPGAs are off-the-shelf chips with a configurable ‘sea’ of logic and memory that can be used to implement digital circuits. FPGAs can be attached to the compute system either through the main system bus or as PCI Express cards (or similar) and are typically configured as highly parallel stream processors. FPGA acceleration has been successfully demonstrated in a variety of application domains including computational finance (Zhang et al., 2005), fluid dynamics (Sano et al., 2007), cryptography (Cheung et al., 2005) and seismic processing (Bean and Gray, 1997; He et al., 2005a; He et al., 2005b; Pell and Clapp, 2007). |
