Research of parallel scheduling strategy for hierarchical SiP test using IEEE 1500 standard

Autor:	Liangliang Liu, Xiongbo Zhao, Jiang Penglong
Rok vydání:	2014
Předmět:	System in package Automatic test equipment Test flow Parallel scheduling Computer science business.industry Embedded system System testing System on a chip business Test (assessment) Access structure
Zdroj:	2014 15th International Conference on Electronic Packaging Technology.
DOI:	10.1109/icept.2014.6922838
Popis:	A SiP(System in Package) consists of multiple chips stacked and connected within a package. And SiP testing is a significant and growing problem owing to the limited accessibility and its particular test flow. It requires individual chip-level, interconnections test, post-packaging test and final system testing. This paper presents an overview of SiP test flow and the problem encountered by SiP test, and suggests its solution — the IEEE 1500 Standard for Embedded Core Test (SECT). IEEE 1500 provides test access structure and mechanisms to implement the parallel scheduling test for hierarchical SiP.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::746520e87f1c6a1c5268dfde307fc267 https://doi.org/10.1109/icept.2014.6922838 Zobrazit plný text záznamu