Evaluation of Design Parameters for Leadless Chip Resistors Solder Joints
| Autor: | Edward Chan-Jiun Jih, Yi-Hsin Pao |
|---|---|
| Rok vydání: | 1995 |
| Předmět: |
Materials science
Physics::Instrumentation and Detectors business.industry Electronic packaging Structural engineering Chip Finite element method Computer Science::Other Computer Science Applications Electronic Optical and Magnetic Materials law.invention Capacitor Reliability (semiconductor) Creep Mechanics of Materials law Soldering Electrical and Electronic Engineering Resistor business |
| Zdroj: | Journal of Electronic Packaging. 117:94-99 |
| ISSN: | 1528-9044 1043-7398 |
| DOI: | 10.1115/1.2792087 |
| Popis: | Failures in electronic packaging under thermal fatigue often result from cracking in solder joints due to creep/fatigue crack growth. A nonlinear, time-dependent finite element analysis was performed to study the effect of critical design parameters on thermal reliability of leadless chip capacitor or resistor solder joints. The shear strain range based on thermal hysteresis response was used to study the sensitivity of various parameters, such as solder stand-off height, fillet geometry, Cu-pad length, and component length and thickness. The results were used as guidelines for designing reliable solder joints. In addition, an analytical model for the solder joint assembly was derived. It can be used .as an engineering approach for rapid assessment of large numbers of design parameters. The accuracy and effectiveness of the analytical model were evaluated by comparing with finite element results. |
| Databáze: | OpenAIRE |
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