Sequential faults and aliasing

Autor:	Tiko Kameda, André Ivanov, Slawomir Pilarski
Rok vydání:	1993
Předmět:	Sequential logic Logic testing Binary number Hardware_PERFORMANCEANDRELIABILITY Integrated circuit Computer Graphics and Computer-Aided Design law.invention Test sequence law Electrical and Electronic Engineering Aliasing (computing) Algorithm Software Mathematics Characteristic polynomial
Zdroj:	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 12:1068-1074
ISSN:	0278-0070
DOI:	10.1109/43.238044
Popis:	Aliasing is studied for delay and stuck-open faults. It is shown that, as the test sequence length is increased, the probability of aliasing for such faults tend to 2/sup -k/, where k is the number of binary memory elements in a linear compactor. The result is based on the assumption that the linear compactor has an irreducible characteristic polynomial. Some recent results on combinational faults are special cases of the results presented here. >
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::7444c1af1609dd831ec215aeae9f18d0 https://doi.org/10.1109/43.238044 Zobrazit plný text záznamu