A 320-fs RMS Jitter and – 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC

Autor:	Taeho Seong, Jaehyouk Choi, Yongsun Lee, Seyeon Yoo
Rok vydání:	2019
Předmět:	Loop (topology) Phase-locked loop Physics DPLL algorithm Hardware_INTEGRATEDCIRCUITS Spur Electronic engineering dBc Hardware_PERFORMANCEANDRELIABILITY Digitally controlled oscillator Electrical and Electronic Engineering Power (physics) Jitter
Zdroj:	IEEE Journal of Solid-State Circuits. 54:2501-2512
ISSN:	1558-173X 0018-9200
Popis:	This paper presents a ring-type, digitally controlled oscillator (DCO)-based integer- ${N}$ digital phase-locked loop (DPLL) that can achieve low jitter and low reference spur concurrently. In order to minimize the quantization error, while consuming a small amount of power, this work presents an optimal-threshold (OT) time-to-digital converter (TDC). The thresholds of the OT TDC and the phase-correction gain of the loop are corrected continuously in the background. The PLL was fabricated in a 65-nm CMOS process and its measured rms jitter integrated from 1 kHz to 100 MHz and the reference spur of a 2.4-GHz frequency were 320 fs and −75 dBc, respectively. Through measurement, they were verified to be maintained robustly over temperature and supply variations. The active area was 0.055 mm2, and the power consumption was 6.0 mW.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::73d6c22232bcdd2b67d7b956946abe2b https://doi.org/10.1109/jssc.2019.2918940 Zobrazit plný text záznamu