| Popis: |
Flash memory is an important driver of the lithography roadmap, with its dramatic acceleration in dimensional shrink, pushing for ever smaller feature sizes. The introduction of hyper-NA immersion lithography has brought the 45nm node and below within reach for memory makers using single exposure. At these feature sizes mask topology and the material properties of the film stack on the mask play an important role on imaging performance. Furthermore, the break up of the array pitch regularity in the NAND-type flash memory cell by two thick wordlines and a central space, leads to feature-center placement (overlay) errors, that are inherent to the design. An integral optimization approach is needed to mitigate these effects and to control both the CD and placement errors tightly. In this paper we will show that aerial image measurements at mask-level are useful for characterizing the gate layer of a NAND-Flash design before exposure. The aerial image measurements are performed with the AIMSTM 45-193i. and compared to CD measurements on the wafer obtained with an XT:1900Gi hyper-NA immersion system. An excellent correlation is demonstrated for feature-center placement errors and CD variations across the mask (see Figure 1) for several features in the gate layer down to 40nm half pitch. This shows the potential to use aerial image measurements at mask-level in combination with correction techniques on the photomask, like the CDC200 tool in combination with exposure tool correction techniques, such as DoseMapperTM, to improve both across field and across wafer CD uniformity of critical layers. |
