| Autor: |
Faizah Abu Bakar, Muhammad Haniff Mehat, Yew Huang Lau |
| Rok vydání: |
2021 |
| Předmět: |
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| Zdroj: |
2021 IEEE Regional Symposium on Micro and Nanoelectronics (RSM). |
| DOI: |
10.1109/rsm52397.2021.9511609 |
| Popis: |
In modern CMOS technologies, interconnect or metallization reliability is part of an assessment for process robustness of the vias and aluminium metal lines. Typically these tests - Electromigration and Stressmigration occurs during process or technology qualification prior to mass production. These wearout test methodologies are also used when systematic interconnect defects are encountered during wafer processing. In this paper, we will illustrate a case whereby defect density at bottom of via holes were encountered. Both wearout tests were carried out to evaluate the risk of shipment to customer. The lifetime of the devices were calculated for Electromigration test whereas for Stressmigration a qualitative assessment was made. The results show that via reliability performance is dependent on type of via defect density encountered. Electromigration and Stressmigration were carried as a complement to product reliability test like High Temperature Operating Life (HTOL) which are limited by sample size for a more complete risk assessment. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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