Methodology for thermal-mechanical modeling of damage and failure processes in through-silicon-vias
| Autor: | M.A.A. Afripin, M.N. Tamin, C. K. Yoon |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Interconnection Materials science Silicon Transistor Constitutive equation chemistry.chemical_element 02 engineering and technology 01 natural sciences 020202 computer hardware & architecture law.invention Stress (mechanics) chemistry law Thermal mechanical 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Shear stress Composite material Deformation (engineering) |
| Zdroj: | 2017 12th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT). |
| DOI: | 10.1109/impact.2017.8255912 |
| Popis: | The reported failure of the Cu-filled via adjacent to the SiO2 liner of a TSV interconnect under thermal-mechanical stressing calls for a thorough quantitative investigation. In this respect, this paper presents a FE-based methodology to quantify the mechanics of deformation and failure processes of the Cu-filled via. The simulation employs Johnson-Cook constitutive model and damage equation to represent the damage response of the TSV interconnect to the temperature changes (ζ1Γ=-125 °C; 5, 15 and 45 °C/min). Results show that the large shear stress and stress gradient in the Cu-filled via adjacent to the SiO2 liner is detrimental to crack initiation. A staggered TSV array with pitch length-to-via diameter of 2 is unable to accommodate any transistor without adversely affecting its performance. |
| Databáze: | OpenAIRE |
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