A 10MHz to 600MHz low jitter CMOS PLL for clock multiplication

Autor:	Luo-sheng Li, Chao-huan Hou, Zi-qiao Chu, Dong-hui Wang, Bing Fan
Rok vydání:	2008
Předmět:	Phase-locked loop Physics Voltage-controlled oscillator CMOS PLL multibit Hardware_INTEGRATEDCIRCUITS Electronic engineering Multiplication Hardware_PERFORMANCEANDRELIABILITY Hardware_ARITHMETICANDLOGICSTRUCTURES Phase frequency detector Power (physics) Jitter
Zdroj:	2008 9th International Conference on Solid-State and Integrated-Circuit Technology.
DOI:	10.1109/icsict.2008.4734970
Popis:	This paper describes a phase-locked loop (PLL) designed for clock multiplication. The PLL has a locking range from 10 MHz to 600 MHz at 1.8 V power supply. It has a very low peak-to-peak jitter which less than 50 ps at 150 MHz output frequency. It has been fabricated in a 0.18 ?m CMOS process. The area of the active layout of the PLL is 560 ?m * 400 ?m, and power consumption is about 6 mW.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::7314a92101869886cfa2ab25a6c9613d https://doi.org/10.1109/icsict.2008.4734970 Zobrazit plný text záznamu