| Autor: |
Chen-Yi Lee, Yu-Cheng Lan, Chih-Lung Chen, Hsie-Chia Chang |
| Rok vydání: |
2013 |
| Předmět: |
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| Zdroj: |
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC). |
| DOI: |
10.1109/asscc.2013.6691005 |
| Popis: |
In this work, a decoder chip for time-invariant tail-biting LDPC convolutional code (TB-LDPC-CC) is proposed. By modifying the layered decoding scheduling, the proposed decoding algorithm can achieve twice faster decoding convergence than the conventional flooding scheduling. Furthermore, 30.77% storage requirement is also reduced due to adaptive channel value addressing employed in memory-based decoder design. The multiple frame sizes handling ability can lower the power and adapt to multiple applications. By integrating these techniques, a TB-LDPC-CC decoder chip supporting three frame sizes is implemented in UMC 90nm CMOS technology. The decoder containing 4 processors occupies 2.18mm2 area and provides maximum throughput 3.66Gb/s under 0.8V supply and 305MHz with a 18.8pJ/bit/proc energy efficiency. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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