An efficient VLSI architecture for rate disdortion optimization in AVS video encoder
| Autor: | Zhe Lei Xia, Hai bing Yin, Xi Zhong Lou, Wen Gao |
|---|---|
| Rok vydání: | 2008 |
| Předmět: |
Very-large-scale integration
business.industry Computer science Quantization (signal processing) Parallel computing Rate–distortion optimization Golomb coding VHDL Discrete cosine transform Common Intermediate Format Redundancy (engineering) business Field-programmable gate array Encoder computer Computer hardware computer.programming_language |
| Zdroj: | ISCAS |
| DOI: | 10.1109/iscas.2008.4542040 |
| Popis: | A dedicated VLSI architecture is proposed to implement rate distortion optimization (RDO) for AVS video coding, with 4CIF format video supported at a system clock of 54 MHZ for low power applications. The seven-step block level pipeline architecture is employed for RDO with parallel structure to satisfy the timing constraint with all coding modes supported in AVS-P2. Fast transform domain SSD calculation algorithm is employed to reduce the computation redundancy in RDO. The run length pair detection and Golomb coding bits estimation modules are implemented using four-way parallel structure with 2D-VLC tables shared mutually. Other modules in the RDO pipeline are implemented with eight-way parallel structure. The architecture is implemented using VHDL language and successfully verified on Xilinx Virtex-2 FPGA. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|