Compiling regular arrays onto FPGAs
| Autor: | C. N. Jordan, William P. Marnane, F. J. O'Reilly |
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| Rok vydání: | 1995 |
| Předmět: |
Interconnection
business.industry Computer science Logic block Systolic array Macrocell array Parallel computing Complex programmable logic device Programmable logic array Computer Science::Hardware Architecture Hardware_ARITHMETICANDLOGICSTRUCTURES Field-programmable gate array business Digital signal processing Computer hardware Hardware_LOGICDESIGN |
| Zdroj: | Field-Programmable Logic and Applications ISBN: 9783540602941 FPL |
| DOI: | 10.1007/3-540-60294-1_111 |
| Popis: | Many DSP functions can be implemented as arrays of simple Processing Elements (PEs) connected to their nearest neighbours in a regular manner. Field Programmable Gate Arrays consist of an array of user-configurable logic blocks and a matrix of user configurable interconnection between the logic blocks. Thus FPGAs are prime candidates for implementing regular arrays. In this paper we present FPGA Regular Array Description Language (FRADL) which will map the regular array into a FPGA. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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