| Autor: |
J.P. Biggs, P.L. Harrod, A.J. Merritt, H.E. Oldham, D.W. Howard, H.L. Watters, A.J. Baum, D.J. Seal |
| Rok vydání: |
2002 |
| Předmět: |
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| Zdroj: |
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93. |
| DOI: |
10.1109/cicc.1993.590407 |
| Popis: |
The FPA10 has been designed to provide balanced floating point performance to complement the integer performance of ARM CPUs (central processing units) while remaining a low-cost and low-power device. Concurrent load/store and arithmetic execution units, speculative execution, and innovative circuit design enable 4 MFLOPS to be achieved with a power dissipation of 250 mW at 5 V. The 134K transistor, 66.7-mm/sup 2/ chip is implemented in 1-/spl mu/m CMOS and is packaged in a low-cost 68-pin PLCC. FPA 10 implements a subset of the ARM floating-point instruction set; other, rarely executed instructions and most exception conditions are handled by software emulation. This has enabled a low-power, low-cost design which provides floating-point performance that is well-matched with the ARM integer performance. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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