Elliptic Curve Cryptography hardware accelerator for high-performance secure servers
| Autor: | Encarnación Castillo, Luis Parrilla, Antonio García, Diego P. Morales-Santos, J. A. López-Ramos, José Antonio Álvarez-Bermejo |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
020203 distributed computing
Coprocessor business.industry Computer science Cryptography 02 engineering and technology Encryption Theoretical Computer Science Hardware and Architecture Server Embedded system Scalability 0202 electrical engineering electronic engineering information engineering Hardware acceleration Elliptic curve cryptography Field-programmable gate array business Software Information Systems |
| Zdroj: | The Journal of Supercomputing. 75:1107-1122 |
| ISSN: | 1573-0484 0920-8542 |
| DOI: | 10.1007/s11227-018-2317-6 |
| Popis: | Security threats affecting electronics communications in the current world make necessary the encryption and authentication of every transaction. The increasing levels of security required are leading to an overload of transaction servers due to cryptographic tasks. In this paper, a hardware-implemented coprocessor for Elliptic Curve Cryptography operations is presented. This coprocessor enables the acceleration of secure services and can be implemented in the last generations FPGA, thus allowing to host in the same chip a software secure web/database server and the cryptographic coprocessor. Obtained results show advantages of the proposed solution when compared to software implementations and classical acceleration using graphics processing units. Moreover, the proposed cryptographic coprocessor presents improvements over other hardware implementations when area, performance and scalability are considered. The developed crypto-processor has been implemented in a xc7z020clg484-1 device from Xilinx, taking advantage of the synergy provided by the ARM microprocessors and the programmable logic for hardware implementations included in the device. This design requires only 9852 LUTs, while providing 8930 scalar-point operations per second when operating at 50 MHz, with a power consumption of 0.42 W. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|
Full text from SpringerLink