New design of an RSFQ parallel multiply–accumulate unit
| Autor: | Anna Kidiyarova-Shevchenko, Irina Kataeva, Henrik Engseth |
|---|---|
| Rok vydání: | 2006 |
| Předmět: |
Josephson effect
Binary tree Computer science Rounding Ripple Metals and Alloys Condensed Matter Physics Topology Base station Rapid single flux quantum VHDL Materials Chemistry Ceramics and Composites Multiplier (economics) Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering computer computer.programming_language |
| Zdroj: | Superconductor Science and Technology. 19:S381-S386 |
| ISSN: | 1361-6668 0953-2048 |
| DOI: | 10.1088/0953-2048/19/5/s45 |
| Popis: | The Multiply-Accumulate Unit (MAC) is a central component of a Successive Interference Canceller, an advanced receiver for W-CDMA base stations. A 4*4 two's complement fixed point RSFQ MAC with rounding to 5 bits has been simulated using VHDL and maximum performance is equal to 24 GMACS (giga multiple-accumulates per second). The clock distribution network has been re-designed from a linear ripple to a binary tree network in order to eliminate data dependence of the clock propagation speed and reduce number of Josephson junctions in clock lines. The 4*4 bits MAC has been designed for the HYPRES 4.5 kA/cm^2 process and its components have been experimentally tested at low frequency: the 5 bit combiner, using an exhaustive test pattern, had margins on DC bias voltage of +-18% and the 4*4 parallel multiplier had margins equal to +-2%. |
| Databáze: | OpenAIRE |
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